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www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 1 38 d atas he et a s 11 30 1 32 - l e d c r o s s -p l e x i n g dr i v e r w i th sc r o l l i n g f u n c ti o n 1 general description the AS1130 is a compact led driver for 132 single leds. the d evices can be programmed via an i2c compatible interface. the AS1130 offers a 12x11 ledmatrix with 1/12 cycle rate. the required lines to drive all 132 leds are reduced to 12 by using the crossplexing feature optimizing space on the pcb. the whole led matrix driving 132 leds can be analog dimmed from 0 to 30ma in 256 steps (8 bit). additionally each of the 132 leds can be dimmed individually with 8 bit allowing 256 steps of linear dimming. to reduce cpu usage up to 6 frames can be stored with individual time delays between frames to play small animations automatically. the AS1130 operates from 2.7v to 5.5v and features a very low shutdown and operational current. the device offers a programmable irq pin. via a register it can be set on what event (cp request, interface time out, errordetection, por, end of frame or end of movie) the iro is triggered. also hardware scroll function is implemented in the AS1130. the device is available in a ultrasmall 20pin wlcsp and an easy to solder 28pin ssop package. figure 1. AS1130 - typical application 2 key features 1mhz i2ccompatible interface open and shorted led error detection 132 leds in dot matrix lowpower shutdown current individual 8bit led pwm control 8bit analog brightness control 8bit dot correction for optimize rgb led operation programmable irq pin scroll function up to 36 frames memory for animations up to 6 frames memory for pwm sets supply voltage range: 2.7v to 5.5v minimum pcb space required available packages: 20pin wlcsp 28pin ssop (planned) 3 applications the AS1130 is ideal for dot matrix displays in mobile phones, per s onal electronic and toys. ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 2 38 AS1130 datasheet p i n o u t 4 pinout p in assignments figure 2. pin assignments (top view) pin descriptions table 1. pin descriptions pin number pin name description 20-pin wl-csp 28-pin ssop a3 1, 7, 14, 22, 28 gnd ground c3 13 rstn reset input . pull this pin to logic low to reset all control registers (set to default values). for normal operation pull this pin to v dd . d 1 17 addr i2c address. connect to external resistor for i2c address selection. up to 8 devices can be connected on one bus. (see table 6 on page 12) d2 16 sd a serial-data i/o . open drain digital i/o i2c data pin. d3 15 scl serial-clock input b3 3, 10, 18, 19, 26 vdd positive supply voltage . connect to a +2.7v to +5.5v supply. bypass this pin with 10f capacitance to gnd. d4 12 sync synchronization clock input or output. the sync frequency for input and output is 1mhz. for sync_out the frequency can be reduced to 32khz. d5 11 irq interrupt request. programmable open drain digital output. it can be set via an register after which event (interface timeout, pok, cp_request, error detection, end of frame or end of movie) the pin triggers an interrupt request. a1, a2, a4, a5, b1, b2, b4, b5, c1, c2, c4, c5 25, 27, 2, 4, 23, 24, 5, 6, 21, 20, 9, 8 cs0, cs1, cs6, cs7, cs2, cs3, cs8, cs9, cs4, cs5, cs10, cs11 sinks and sources for 132 leds. 20pin wlcsp 28pin ssop ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 3 38 AS1130 datasheet a b s o l u t e m a x i m u m r a t i n g s 5 absolute maximum ratings stresses beyond those listed in t able 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in section 6 electrical characteristics on page 4 is not implied. ex posure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units comments electrical parameters vdd to gnd 0.3 7 v all other pins to gnd 0.3 7 or v dd + 0.3 v s ink current 500 ma segment current 100 ma input current (latchup immunity) 100 100 ma norm: jedec 78 electrostatic discharge electrostatic discharge hbm 2 kv norm: mil 883 e method 3015 temperature ranges and storage conditions junction temperature +150 oc storage temperature range 55 +125 oc for 20pin wlcsp 55 +150 oc for 28pin ssop package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/jedec j-std-020moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices. the lead finish for pbfree leaded packages is matte tin (100% sn). humidity noncondensing 5 85 % moisture sensitive level 1 20pin wlcsp represents a max. floor life time of unlimited 3 28pin ssop represents a max. floor life time of 168h ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 4 38 AS1130 datasheet e l e c t r i c a l c h a r a c t e r i s t i c s 6 electrical characteristics v dd = 2.7v to 5.5v, typ. values are at t amb = +25oc (unless otherwise specified). all limits are guaranteed. the parameters with min and max values are guaranteed with production tests or sqc (statistical quality control) methods. table 3. electrical characteristics symbol parameter conditions min typ max unit t amb operating temperature range 40 85 c t j operating junction temperature range 40 125 c v dd operating supply voltage 2 .7 5.5 v i dd operating supply current a ll current sources turned on @ v dd = 5.5v 3 40 ma all current sources turned off @ v dd = 5.5v 0 .5 i ddssd software shutdown supply current a ll digital inputs at v dd or gnd @ v dd = 5.5v 7 15 a i ddfsd full shutdown supply current pin rstn = 0v, t amb = +25oc 0 .1 1 a i digit digit drive sink current ( drive capability of all sources of one digit 1 ) 1. guaranteed by design 360 ma i seg segment drive source current led 2 2. v out = 1.8v to v dd 400mv 2 8 30 32 ma d i seg segment drive current matching led 1 % device to device current matching led v out = 1.8v, v dd = 3.3v 1 % i leak leakage output current a ll current sources off, v out = 0v, v dd = 5.5v, t amb = +25oc 0 .005 0.5 a d i lnr line regulation v out = 1.8v 0 .25 %/v d i ldr load regulation v out = 1.8v to v dd 400mv 0 .25 %/v v dssat saturation voltage c urrent = 30ma, v dd = 3.3v 2 00 mv r dson(n) resistance for nmos 0.3 1 w open detection level threshold v dd 0 .4 v dd 0 .1 v short detection level threshold 770 900 mv f osc oscillator frequency 0 .9 1 1.1 mhz f refresh display scan rate 1 2x11 matrix 0.29 0.33 0.36 khz t rstn reset pulse width low 5 00 ns i seg i max i min C i max i min + - -------------------------- 100 = ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 5 38 AS1130 datasheet e l e c t r i c a l c h a r a c t e r i s t i c s note: t he min / max values of the timing characteristics are guaranteed by design. table 4. logic inputs/outputs characteristics symbol parameter conditions min typ max unit i ih , i il logic input current v in = 0v or v dd 1 1 a v ih cmos logic high input voltage 0 .7 x v dd v v il cmos logic low input voltage 0 .3 x v dd v d v i cmos hysteresis voltage 0 .3 v v ih mobile logic high input voltage 1 1.6 v v il mobile logic low input voltage 1 0.6 v d v i hysteresis voltage 1 0.1 v v ol(sda) sda output low voltage i sink = 3ma 0 .4 v v ol(irq) irq output low voltage i sink = 3ma 0 .4 v v ol(sync_ o ut) sync clock output low voltage i sink = 1ma 0 .4 v v oh(sync _ out) sync clock output high voltage i source = 1ma v dd 0.4 v c apacitive load for each bus line 400 pf 1. available on request, see ordering information on page 37 table 5. i2c timing characteristics symbol parameter conditions min typ max unit f scl scl frequency 1 00 1000 khz t buf bus free time between stop and start conditions 1 .3 s t holdstart hold time for repeated s tart condition 260 ns t low scl low period 5 00 ns t high scl high period 2 60 ns t setupstart setup time for repeated s tart condition 260 ns t setupdata data setup time 1 00 ns t holddata data hold time 7 0 ns t rise(scl) scl rise time 1 20 ns t rise(scl1) scl rise time after repeated start condition and after a n ack bit 120 ns t fall(scl) scl fall time 1 20 ns t rise(sda) sda rise time 1 20 ns t fall(sda) sda fall time 1 20 ns t setupstop stop condition setup time 2 60 ns t spikesup pulse width of spike suppressed 6 ns ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 6 38 AS1130 datasheet e l e c t r i c a l c h a r a c t e r i s t i c s figure 3. timing diagram repeated start sdi scl start stop t buf t low t holdstart t holddata t r t high t f t setupdata t holdstart t spikesup t setupstop t setupstart ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 7 38 AS1130 datasheet ty p i c a l o p e r a t i n g c h a r a c t e r i s t i c s 7 typical operating characteristics figure 4. segment drive current vs. supply voltage f igure 5. segment drive current vs. temperature 28 28.5 29 29.5 30 30.5 31 31.5 32 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 segment drive source current (ma) supply voltage (v) -45c +25c +85c 28 28.5 29 29.5 30 30.5 31 31.5 32 -45 -25 -5 15 35 55 75 segment drive source current (ma) temperature ( c) vdd = 2.7v vdd = 3.3v vdd = 4.5v vdd = 5.5v figure 6. segment drive current vs. output voltage figure 7. r onnmos vs. s upply voltage 28 28.5 29 29.5 30 30.5 31 31.5 32 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 segment drive source current (ma) output voltage (v) vdd = 2.7v vdd = 3.3v vdd = 4.5v vdd = 5.5v 0 0.1 0.2 0.3 0.4 0.5 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 r nmos ( ) supply voltage (v) -45c +25c +85c figure 8. open detection level vs. supply voltage figure 9. short detection level vs. supply voltage 0 50 100 150 200 250 300 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 open detection level (mv) supply voltage (v) -45c +25c +85c 0.6 0.65 0.7 0.75 0.8 0.85 0.9 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 short detection level (v) supply voltage (v) -45c +25c +85c ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 8 38 AS1130 datasheet ty p i c a l o p e r a t i n g c h a r a c t e r i s t i c s figure 10. cmos logic input levels vs. s upply voltage figure 11. cmos logic input levels vs. temperature 0 0.5 1 1.5 2 2.5 3 3.5 4 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 logic input voltage level (v) supply voltage (v) logic high logic low 0 0.5 1 1.5 2 2.5 3 3.5 4 -45 -25 -5 15 35 55 75 logic input voltage level (v) temperature ( c) logic high logic low figure 12. mobile logic input levels vs. supply voltage figure 13. mobile logic input levels vs. temperature 0 0.5 1 1.5 2 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 logic input voltage level (v) supply voltage (v) logic high logic low 0 0.5 1 1.5 2 -45 -25 -5 15 35 55 75 logic input voltage level (v) temperature ( c) logic high logic low figure 14. oscillator frequency vs. supply voltage figure 15. oscillator frequency vs. temperature 0.9 0.95 1 1.05 1.1 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 f osc (khz) supply voltage (v) - 45c + 25c + 85c 0.9 0.95 1 1.05 1.1 -45 -25 -5 15 35 55 75 f osc (khz) temperature ( c) vdd = 2.7v vdd = 3.3v vdd = 4.5v vdd = 5.5v ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 9 38 AS1130 datasheet d e t a i l e d d e s c r i p t i o n 8 detailed description figure 16. AS1130 - block diagram cross-plexing theorem the crossplexing theorem is using the fact that a led has a forward and backward direction. a led will only glow if there is a current flowing in f orward direction. a parallel led in backward direction will block the current flow. this effect is used in a crossplexed matrix of leds. each csx pin (cs0 to cs11) can be switched to vdd via the internal current source (high), to gnd (low) or not connected (highz). the mode of operation which is controlled by an internal state machine looks like following. cs0 is switched to gnd and all other csx pins (cs1 to cs11) are controlled according to the settings in the on/off frame and blink & pwm registers (see table 7 on page 14) . th an cs1 is switched to gnd and all other csx pins (cs0 and cs2 to cs11) are controlled according to the settings in the on/off frame and blink & pwm registers. in this manner all leds in the matrix are scanned and turned on/off depending on the register settings. ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 10 38 AS1130 datasheet d e t a i l e d d e s c r i p t i o n i2c interface the AS1130 supports the i2c serial bus and data transmission protocol in fast mode at 1mhz. the AS1130 operates as a slave on the i2c bus. t he bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. connections to the bus are made via the opendrain i/o pins scl and sda. figure 17. i2c interface initialization figure 18. bus protocol the bus protocol (as shown in figure 18 ) is defined as: d ata transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. the bus conditions are defined as: bus not busy . data and clock lines remain high. start data transfer . a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfe r. a change in the state of the data line, from low to high, while the clock line is high, defines the stop condition. data valid . the state of the data line represents valid data, when, after a start condition, the data line is stable for the duration of the high period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and termi nated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. the information is transferred bytewise and each receiver acknowledges with a ninthbit. within the i2c bus speci fications a highspeed mode (3.4mhz clock rate) is defined. acknowledge : each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the mas ter device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generat ing an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. figure 18 on page 10 details how data transfer is accomplished on the i2 c bus. depending upon the state of the r/w bit, two types of data transfer are possible: 1 98 1 98 10 ad2 1 0 ad1 ad0 r/w d15 d14 d13 d12 d11 d10 d9 d8 ad2, ad1 and ad0 are defined by the pin addr (see i2c device address byte on page 12) scl sda sdi scl slave address r/w direction bit start 1 2 6 7 8 9 1 2 3-7 8 9 ack msb repeat if more bytes transferred stop or repeated start ack from receiver ack from receiver ack ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 11 38 AS1130 datasheet d e t a i l e d d e s c r i p t i o n m aster transmitter to slave receiver . the first byte transmitted by the master is the slave address, followed by a number of data bytes. the slave returns an acknowledge bit after the slave address and each received byte. slave transmitter to master receiver . the first byte, the slave address, is transmitted by the master. the slave then returns an acknowl edge bit. next, a number of data bytes are transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a notacknowledge is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. the AS1130 can operate in the following slave modes: slave receiver mode . serial data and clock are received through sda and scl. after each byte is received, an acknowledge bit is trans mitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. slave transmitter mode . the first byte (the slave address) is received and handled as in the slave receiver mode. however, in this mode the direction bit will indicate that the transfer direction is reversed. serial data is transmitted on sda by the AS1130 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. command byte the AS1130 operation, ( see table 13 on page 20) is determined by a command byte (see table 19) . fi gure 19. command byte figure 20. command and single data byte received by AS1130 figure 21. setting the pointer to a address register to select a data register for a read operation a7 a6 a5 a4 a3 a2 a1 a0 msb 6 5 4 3 2 1 lsb from master to slave from slave to master a a p a s command byte data byte slave address a6 a5 a4 a3 a2 a1 a0 a7 d6 d5 d4 d3 d2 d1 d0 d7 acknowledge from AS1130 0 0 0 acknowledge from AS1130 acknowledge from AS1130 r/w 0 AS1130 registers autoincrement memory word address 1 byte from master to slave from slave to master a p a s command byte slave address a6 a5 a4 a3 a2 a1 a0 a7 0 0 acknowledge from AS1130 acknowledge from AS1130 r/w 0 AS1130 registers ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 12 38 AS1130 datasheet d e t a i l e d d e s c r i p t i o n figure 22. reading n bytes from AS1130 i2c device address byte the address byte ( see figure 23) is the first byte received following the start condi tion from the master device. figure 23. i2c device address byte the bit 1, 2 and 3 of the address byte are defined through the resistor @ the device select pin addr (see table 6 on page 12) . a m a ximum of 8 devices with the same preset code can be connected on the same bus at one time. the last bit of the address byte (r/w ) define the operation to be performed. when set to a 1 a read operation is selected; when set to a 0 a write operation is selected. i2c common address. all devices are responding on the address 0111111 if the function is enabled in the register AS1130 config re gister (0x06) on page 25 . fo llowing the start condition, the AS1130 monitors the i2c bus, checking the device type identifier being transmitted. upon receiving the address code, and the r/w bit, the slave device outputs an acknowledge signal on the sda line. the pin addr is scanned after start up (por) and defines the address for the device. the device reacts to this address until a hardware reset (low on pin rstn) is performed or the poweronreset (por) triggers again. note: the internal address decoder needs 5ms to identify the address and to set up the device for this address. table 6. device address i2c address bit bit name default access description 3:1 i2c_addr 000 r defines the i2c address of one device via an external resistor on pin addr 000: 1m w or floating 001: 470k w 010: 220k w 011: 100k w 100: 47k w 101: 22k w 110: 10k w 111: 4.7k w or gnd from master to slave from slave to master a /a p a s first data byte second data byte slave address d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 not acknowledge from master 0 1 0 acknowledge from master acknowledge from AS1130 r/w 1 AS1130 registers autoincrement memory word address n bytes autoincrement to next address stop reading 0 1 1 0* ad2 ad1 ad0 r/w msb 6 5 4 3 2 1 lsb address: *) can be factory set to 1 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 13 38 AS1130 datasheet d e t a i l e d d e s c r i p t i o n initial power-up on initial powerup, the AS1130 registers are reset to their default values, the display is blanked, and the device goes into shutdown mode. at t his time, all registers should be programmed for normal operation. to bring the device into normal operation the following sequence needs to be performed. start-up sequence: powerup the AS1130 (connect vdd to a source), the devices is in shutdown; after 5ms the address of the AS1130 is valid and the first i2c command can be send. define ram configuration; bit mem_conf in the AS1130 config register (see table 20 on page 25) on/off frames blink & pwm sets dot correction, if specified define control register (see table 13 on page 20) current source display options display picture / play movie to light up the leds set the shdn bit to 1 for normal operation mode (see table 23 on page 26) . shutdown mode the AS1130 device features two different shutdown modes. a software shutdown via shutdown register ( see shutdown & open/short re gister format on page 26) and a hardware shutdown via the rstn pin. th e software shutdown disables all leds and stops the internal operation of the logic. a shutdown mode via the rstn pin additionally powers down the poweronreset (por) of the device. in this shutdown mode the AS1130 consumes only 100na (typ.). ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 14 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n 9 register description r egister selection within this register the access to one of the ram sections, the dot correction or to the control register is selected. after one section is selected t his section is valid as long as an other section is selected. data definition of the single frames one frame consists of 2 datasets, the on/off dataset and the blink & pwm dataset. where more on/off frames can be linked to one pwm set. d epending on the used pwm sets more or less on/off frames can be stored inside the AS1130 (see table 8) . ea ch on/off frame needs to define the used blink & pwm dataset. its necessary to define the ram configuration before data can be written to the frame datasets. the ram configuration is defined in the AS1130 config register (see table 20 on page 25) via bit 2:0 and bit 4 for dot correction. n o te: after a first write of data to the frames, the configuration is locked in the AS1130 config register and can be changed only after a reset of the device. a change of the ram configuration requires to rewrite the frame datasets. table 7. register selection address map register section address data description hex a7 a6 a5 a4 a3 a2 a1 a0 hex d7 d6 d5 d4 d3 d2 d1 d0 nop 0xfd 1 1 1 1 1 1 0 1 0x00 0 0 0 0 0 0 0 0 no operation on/off frame 0 0x01 0 0 0 0 0 0 0 1 on/off information for each frame (up to 36 frames) on/off frame 1 0x02 0 0 0 0 0 0 1 0 on/off frame 2 0x03 0 0 0 0 0 0 1 1 .... ..... on/off frame 34 0x23 0 0 1 0 0 0 1 1 on/off frame 35 0x24 0 0 1 0 0 1 0 0 blink & pwm set 0 0x40 0 1 0 0 0 0 0 0 blink & pwm information sets (up to 6 sets) blink & pwm set 1 0x41 0 1 0 0 0 0 0 1 blink & pwm set 2 0x42 0 1 0 0 0 0 1 0 blink & pwm set 3 0x43 0 1 0 0 0 0 1 1 blink & pwm set 4 0x44 0 1 0 0 0 1 0 0 blink & pwm set 5 0x45 0 1 0 0 0 1 0 1 dot correction 0x80 1 0 0 0 0 0 0 0 selection of dot correction register control register 0xc0 1 1 0 0 0 0 0 0 selection of control register table 8. ram configuration ram configuration blink & pwm sets on/off frames on/off frames with dot correction 1 1 36 35 2 2 30 29 3 3 24 23 4 4 18 17 5 5 12 11 6 6 6 5 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 15 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n 12x11 led matrix the AS1130 is configured to control one big led matrix. f igure 24. AS1130 - dot matrix structure in table 9 its described which databit represents which led i n the matrix. per default all databits are 0, meaning no led is on. a 1 puts the led on. each current segment of the led matrix consists of 11 leds, therefore 2 bytes of data are required for one current segment. cs0 is defined by the two bytes with address 0x00 and 0x01 and also includes the address of the used blink & pwm dataset for this frame. table 9. leds on/off frame register format segment address data hex a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0x00 0 0 0 0 0 0 0 0 led 07 led 06 led 05 led 04 led 03 led 02 led 01 led 00 0x01 0 0 0 0 0 0 0 1 pwm [2] pwm [1] pwm [0] x x led 0a led 09 led 08 1 0x02 0 0 0 0 0 0 1 0 led 17 led 16 led 15 led 14 led 13 led 12 led 11 led 10 0x03 0 0 0 0 0 0 1 1 x x x x x led 1a led 19 led 18 2 0x04 0 0 0 0 0 1 0 0 led 27 led 26 led 25 led 24 led 23 led 22 led 21 led 20 0x05 0 0 0 0 0 1 0 1 x x x x x led 2a led 29 led 28 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 16 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n the blink & pwm sets contain blink on/off and the digital pwm information for each led in the matrix. the number of pwm datasets is flexible a ccording to the defined ram configuration ( see figure 8 on page 14 ). in the blink register (see table 10) every single led can be set to blink. the blink peri od is set in the display option register (see display op tion register format on page 24) . 3 0x06 0 0 0 0 0 1 1 0 led 37 led 36 led 35 led 34 led 33 led 32 led 31 led 30 0x07 0 0 0 0 0 1 1 1 x x x x x led 3a led 39 led 38 4 0x08 0 0 0 0 1 0 0 0 led 47 led 46 led 45 led 44 led 43 led 42 led 41 led 40 0x09 0 0 0 0 1 0 0 1 x x x x x led 4a led 49 led 48 5 0x0a 0 0 0 0 1 0 1 0 led 57 led 56 led 55 led 54 led 53 led 52 led 51 led 50 0x0b 0 0 0 0 1 0 1 1 x x x x x led 5a led 59 led 58 6 0x0c 0 0 0 0 1 1 0 0 led 67 led 66 led 65 led 64 led 63 led 62 led 61 led 60 0x0d 0 0 0 0 1 1 0 1 x x x x x led 6a led 69 led 68 7 0x0e 0 0 0 0 1 1 1 0 led 77 led 76 led 75 led 74 led 73 led 72 led 71 led 70 0x0f 0 0 0 0 1 1 1 1 x x x x x led 7a led 79 led 78 8 0x10 0 0 0 1 0 0 0 0 led 87 led 86 led 85 led 84 led 83 led 82 led 81 led 80 0x11 0 0 0 1 0 0 0 1 x x x x x led 8a led 89 led 88 9 0x12 0 0 0 1 0 0 1 0 led 97 led 96 led 95 led 94 led 93 led 92 led 91 led 90 0x13 0 0 0 1 0 0 1 1 x x x x x led 9a led 99 led 98 a 0x14 0 0 0 1 0 1 0 0 led a7 led a6 led a5 led a4 led a3 led a2 led a1 led a0 0x15 0 0 0 1 0 1 0 1 x x x x x led aa led a9 led a8 b 0x16 0 0 0 1 0 1 1 0 led b7 led b6 led b5 led b4 led b3 led b2 led b1 led b0 0x17 0 0 0 1 0 1 1 1 x x x x x led ba led b9 led b8 table 10. leds blink frame register format segment address data hex a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0x00 0 0 0 0 0 0 0 0 led 07 led 06 led 05 led 04 led 03 led 02 led 01 led 00 0x01 0 0 0 0 0 0 0 1 x x x x x led 0a led 09 led 08 1 0x02 0 0 0 0 0 0 1 0 led 17 led 16 led 15 led 14 led 13 led 12 led 11 led 10 0x03 0 0 0 0 0 0 1 1 x x x x x led 1a led 19 led 18 table 9. leds on/off frame register format segment address data hex a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 17 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n 2 0 x04 0 0 0 0 0 1 0 0 led 27 led 26 led 25 led 24 led 23 led 22 led 21 led 20 0x05 0 0 0 0 0 1 0 1 x x x x x led 2a led 29 led 28 3 0x06 0 0 0 0 0 1 1 0 led 37 led 36 led 35 led 34 led 33 led 32 led 31 led 30 0x07 0 0 0 0 0 1 1 1 x x x x x led 3a led 39 led 38 4 0x08 0 0 0 0 1 0 0 0 led 47 led 46 led 45 led 44 led 43 led 42 led 41 led 40 0x09 0 0 0 0 1 0 0 1 x x x x x led 4a led 49 led 48 5 0x0a 0 0 0 0 1 0 1 0 led 57 led 56 led 55 led 54 led 53 led 52 led 51 led 50 0x0b 0 0 0 0 1 0 1 1 x x x x x led 5a led 59 led 58 6 0x0c 0 0 0 0 1 1 0 0 led 67 led 66 led 65 led 64 led 63 led 62 led 61 led 60 0x0d 0 0 0 0 1 1 0 1 x x x x x led 6a led 69 led 68 7 0x0e 0 0 0 0 1 1 1 0 led 77 led 76 led 75 led 74 led 73 led 72 led 71 led 70 0x0f 0 0 0 0 1 1 1 1 x x x x x led 7a led 79 led 78 8 0x10 0 0 0 1 0 0 0 0 led 87 led 86 led 85 led 84 led 83 led 82 led 81 led 80 0x11 0 0 0 1 0 0 0 1 x x x x x led 8a led 89 led 88 9 0x12 0 0 0 1 0 0 1 0 led 97 led 96 led 95 led 94 led 93 led 92 led 91 led 90 0x13 0 0 0 1 0 0 1 1 x x x x x led 9a led 99 led 98 a 0x14 0 0 0 1 0 1 0 0 led a7 led a6 led a5 led a4 led a3 led a2 led a1 led a0 0x15 0 0 0 1 0 1 0 1 x x x x x led aa led a9 led a8 b 0x16 0 0 0 1 0 1 1 0 led b7 led b6 led b5 led b4 led b3 led b2 led b1 led b0 0x17 0 0 0 1 0 1 1 1 x x x x x led ba led b9 led b8 table 10. leds blink frame register format segment address data hex a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 18 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n in the pwm register (see table 11) the brightness of every single led can be set via a 8bit pwm (255 steps). table 11. leds pwm register format segment address data hex a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 led00 0x18 0 0 0 1 1 0 0 0 255 steps for intensity each single led led01 0x19 0 0 0 1 1 0 0 1 led02 0x1a 0 0 0 1 1 0 1 0 led03 0x1b 0 0 0 1 1 0 1 1 led04 0x1c 0 0 0 1 1 1 0 0 led05 0x1d 0 0 0 1 1 1 0 1 led06 0x1e 0 0 0 1 1 1 1 0 led07 0x1f 0 0 0 1 1 1 1 1 led08 0x20 0 0 1 0 0 0 0 0 led09 0x21 0 0 1 0 0 0 0 1 led0a 0x22 0 0 1 0 0 0 1 0 1 led10 0x23 0 0 1 0 0 0 1 1 255 steps for intensity each single led led11 0x24 0 0 1 0 0 1 0 0 led12 0x25 0 0 1 0 0 1 0 1 led13 0x26 0 0 1 0 0 1 1 0 led14 0x27 0 0 1 0 0 1 1 1 led15 0x28 0 0 1 0 1 0 0 0 led16 0x29 0 0 1 0 1 0 0 1 led17 0x2a 0 0 1 0 1 0 1 0 led18 0x2b 0 0 1 0 1 0 1 1 led19 0x2c 0 0 1 0 1 1 0 0 led1a 0x2d 0 0 1 0 1 1 0 1 2 led20 0x2e 0 0 1 0 1 1 1 0 255 steps for intensity each single led led21 0x2f 0 0 1 0 1 1 1 1 led22 0x30 0 0 1 1 0 0 0 0 led23 0x31 0 0 1 1 0 0 0 1 led24 0x32 0 0 1 1 0 0 1 0 led25 0x33 0 0 1 1 0 0 1 1 led26 0x34 0 0 1 1 0 1 0 0 led27 0x35 0 0 1 1 0 1 0 1 led28 0x36 0 0 1 1 0 1 1 0 led29 0x37 0 0 1 1 0 1 1 1 led2a 0x38 0 0 1 1 1 0 0 0 3 led30 0x39 0 0 1 1 1 0 0 1 255 steps for intensity each single led led31 0x3a 0 0 1 1 1 0 1 0 led32 0x3b 0 0 1 1 1 0 1 1 led33 0x3c 0 0 1 1 1 1 0 0 led34 0x3d 0 0 1 1 1 1 0 1 led35 0x3e 0 0 1 1 1 1 1 0 led36 0x3f 0 0 1 1 1 1 1 1 led37 0x40 0 1 0 0 0 0 0 0 led38 0x41 0 1 0 0 0 0 0 1 led39 0x42 0 1 0 0 0 0 1 0 led3a 0x43 0 1 0 0 0 0 1 1 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 19 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n 4 l ed40 0x44 0 1 0 0 0 1 0 0 255 steps for intensity each single led led41 0x45 0 1 0 0 0 1 0 1 led42 0x46 0 1 0 0 0 1 1 0 led43 0x47 0 1 0 0 0 1 1 1 led44 0x48 0 1 0 0 1 0 0 0 led45 0x49 0 1 0 0 1 0 0 1 led46 0x4a 0 1 0 0 1 0 1 0 led47 0x4b 0 1 0 0 1 0 1 1 led48 0x4c 0 1 0 0 1 1 0 0 led49 0x4d 0 1 0 0 1 1 0 1 led4a 0x4e 0 1 0 0 1 1 1 0 5 led50 0x4f 0 1 0 0 1 1 1 1 255 steps for intensity each single led led51 0x50 0 1 0 1 0 0 0 0 led52 0x51 0 1 0 1 0 0 0 1 led53 0x52 0 1 0 1 0 0 1 0 led54 0x53 0 1 0 1 0 0 1 1 led55 0x54 0 1 0 1 0 1 0 0 led56 0x55 0 1 0 1 0 1 0 1 led57 0x56 0 1 0 1 0 1 1 0 led58 0x57 0 1 0 1 0 1 1 1 led59 0x58 0 1 0 1 1 0 0 0 led5a 0x59 0 1 0 1 1 0 0 1 ................ a leda0 0x86 1 0 0 0 0 1 1 0 255 steps for intensity each single led leda1 0x87 1 0 0 0 0 1 1 1 leda2 0x88 1 0 0 0 1 0 0 0 leda3 0x89 1 0 0 0 1 0 0 1 leda4 0x8a 1 0 0 0 1 0 1 0 leda5 0x8b 1 0 0 0 1 0 1 1 leda6 0x8c 1 0 0 0 1 1 0 0 leda7 0x8d 1 0 0 0 1 1 0 1 leda8 0x8e 1 0 0 0 1 1 1 0 leda9 0x8f 1 0 0 0 1 1 1 1 leda0 0x90 1 0 0 1 0 0 0 0 b ledb0 0x91 1 0 0 1 0 0 0 1 255 steps for intensity each single led ledb1 0x92 1 0 0 1 0 0 1 0 ledb2 0x93 1 0 0 1 0 0 1 1 ledb3 0x94 1 0 0 1 0 1 0 0 ledb4 0x95 1 0 0 1 0 1 0 1 ledb5 0x96 1 0 0 1 0 1 1 0 ledb6 0x97 1 0 0 1 0 1 1 1 ledb7 0x98 1 0 0 1 1 0 0 0 ledb8 0x99 1 0 0 1 1 0 0 1 ledb9 0x9a 1 0 0 1 1 0 1 0 ledba 0x9b 1 0 0 1 1 0 1 1 table 11. leds pwm register format segment address data hex a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 20 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n dot correction register the AS1130 offers a feature to define a correction factor for the analog current for every segment. this correction factor is called dot correction a nd is defined in the dot correction register (see table 12) . the dot correction register is selected via data 12 8 on addr 253. control-registers the AS1130 device contains 14 controlregisters which are listed in table 13 . all registers are selected using a 8bit address wo rd, and com munication is done via the serial interface. select the control register via the register selection (see table 7 on page 14) . th e control register is selected via data 192 on addr 253. table 12. dot correction register format segment address data hex a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0x00 0 0 0 0 0 0 0 0 8 bit dot correction 1 0x01 0 0 0 0 0 0 0 1 8 bit dot correction 2 0x02 0 0 0 0 0 0 1 0 8 bit dot correction 3 0x03 0 0 0 0 0 0 1 1 8 bit dot correction 4 0x04 0 0 0 0 0 1 0 0 8 bit dot correction 5 0x05 0 0 0 0 0 1 0 1 8 bit dot correction 6 0x06 0 0 0 0 0 1 1 0 8 bit dot correction 7 0x07 0 0 0 0 0 1 1 1 8 bit dot correction 8 0x08 0 0 0 0 1 0 0 0 8 bit dot correction 9 0x09 0 0 0 0 1 0 0 1 8 bit dot correction a 0x0a 0 0 0 0 1 0 1 0 8 bit dot correction b 0x0b 0 0 0 0 1 0 1 1 8 bit dot correction table 13. control register address map register name hex register address register data a7 a6 a5 a4 a3 a2 a1 a0 d7:d0 picture 0x00 0 0 0 0 0 0 0 0 (see table 14 on page 21) movie 0x01 0 0 0 0 0 0 0 1 (see table 15 on page 21) movie mode 0x02 0 0 0 0 0 0 1 0 (see table 16 on page 22) frame time / scroll 0x03 0 0 0 0 0 0 1 1 (see table 17 on page 23) display option 0x04 0 0 0 0 0 1 0 0 (see table 18 on page 24) current source 0x05 0 0 0 0 0 1 0 1 (see table 19 on page 24) AS1130 config 0x06 0 0 0 0 0 1 1 0 (see table 20 on page 25) interrupt mask 0x07 0 0 0 0 0 1 1 1 (see table 21 on page 25) interrupt frame definition 0x08 0 0 0 0 1 0 0 0 (see table 22 on page 26) shutdown & open/short 0x09 0 0 0 0 1 0 0 1 (see table 23 on page 26) i2c interface monitoring 0x0a 0 0 0 0 1 0 1 0 (see table 24 on page 27) clk synchronization 0x0b 0 0 0 0 1 0 1 1 (see table 25 on page 27) interrupt status 0x0e 0 0 0 0 1 1 0 0 (see table 26 on page 28) AS1130 status 0x0f 0 0 0 0 1 1 0 1 (see table 27 on page 29) open led 0x 20 0 0 1 0 0 0 0 0 (see table 28 on page 29) ........................ 0x 37 0 0 1 1 0 1 1 1 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 21 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n picture register (0x00) in this register it must be set if a picture is to display on the led matrix or not. also the address of the picture which should be displayed must be s et withi n this register. the default setting of this register is 0x00. note: the display_pic bit (bit 6 in picture register) has lower priority than the display_movie bit (bit 6 in movie register). movie register (0x01) in this register it must be set if a movie is to display on the led matrix or not. also the address of the first frame in the movie needs be set within t his register. the default setting of this register is 0x00. note: the display_movie bit (bit 6 in movie register) has higher priority than the display_pic bit (bit 6 in picture register). table 14. picture register format 0x00 picture register bit bit name default access bit description 7 blink_pic 0 r/w all leds in blink mode during display picture 0: no blink 1: all leds blink 6 display_pic 0 r/w display picture 0: no picture 1: display picture 5:0 pic_addr 000000 r/w address of picture 000000: frame 0 000001: frame 1 000010: frame 2 000011: frame 3 000100: frame 4 000101: frame 5 ............... 100000: frame 32 100001: frame 33 100010: frame 34 100011: frame 35 table 15. movie register format 0x01 movie register bit bit name default access bit description 7 blink_movie 0 r/w all leds in blink mode during play movie 0: no blink 1: all leds blink 6 display_movie 0 r/w 0: no movie 1: start movie 5:0 movie_addr 000000 r/w address of first frame in movie 000000: frame 0 000001: frame 1 000010: frame 2 000011: frame 3 000100: frame 4 000101: frame 5 ............... 100000: frame 32 100001: frame 33 100010: frame 34 100011: frame 35 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 2 2 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n movie mode register (0x02) within this register two movie play options can be set. per default this register is set to 0x00. in scroll mode a movie can stop with the last frame of the movie or scroll endless the number of frames to play in a movie table 16. movie mode register format 0x02 movie mode register bit bit name default access bit description 7 blink_en 0 r/w led blink option 1 0: enabled 1: disabled 1. disable blink option overrides any blink definition in pwm data definition or global blink definition in picture register & movie register bit 7. 6 end_last 0 r/w defines at which frame a movie stops in scroll mode 0: movie ends with 1st frame 1: movie ends with last frame 5:0 movie_frames 000000 r/w number of frames played in a movie, starting at movie_addr defined in movie register 000000: play 1 frame 000001: play 2 frames 000010: play 3 frames 000011: play 4 frames 000100: play 5 frames 000101: play 6 frames ............... 100000: play 33 frames 100001: play 34 frames 100010: play 35 frames 100011: play 36 frames ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 2 3 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n frame time/scroll register (0x03) every single frame in a movie is displayed for a certain time before the next frame is displayed. this time can be set within this register with 4 bits. the stated values in table 17 are typical values. a lso the scroll options are set within this register. per default this register is set to 0x00. table 17. frame time/scroll register format 0x03 frame time/scroll register bit bit name default access bit description 7 frame_fad 0 r/w fade frame option (not available in 5 led block configuration) 0: no fading 1: fading of a frame 6 scroll_dir 0 r/w scroll direction 0: scroll to right 1: scroll to left 5 block_size 0 r/w define block size for scrolling 0: scroll in full matrix 1: scroll in 5 led blocks (current sources split in 2 sections, see scroll f unction on page 31 ) 4 enable scrolling 0 r/w scroll digits at play movie 0: no scrolling 1: scrolling digits at play movie 3:0 frame_delay 0000 r/w delay between frame change in a movie 0000: play frame only one time 0001: 32.5ms 0010: 65ms 0011: 97.5ms 0100: 130ms 0101: 162.5ms 0110: 195ms 0111: 227.5ms 1000: 260ms 1001: 292.5ms 1010: 325ms 1011: 357.5ms 1100: 390ms 1101: 422.5ms 1110: 455ms 1111: 487.5ms ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 2 4 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n display option register (0x04) in this register the number of loops in a movie are defined. with the scanlimit it can be controlled how many digits are displayed in each matrix. when all 12 digits in the matrix are displayed, the display scan rate is 430hz (typ.). if the number of digits to display is reduced, the update fre quency is increased. per default this register is set to 0x20. note: to stop a movie in play endless mode, bits d7:d5 have to be set to a value between 000 to 110. current source register (0x05) within this registers the current for every single led can be set from 0ma to 30ma in 255 steps (8 bits). per default this register is set to 0x00. table 18. display option register format 0x04 display option register bit bit name default access bit description 7:5 loops 001 r/w number of loops played in one movie 000: not valid 001: 1 loop 010: 2 loops 011: 3 loops 100: 4 loops 101: 5 loops 110: 6 loops 111: play movie endless (needs to be reset to 06 to stop movie); for scroll endless set bit end_last = 0 4 blink_freq 0 r/w blink period 0: 1.5s 1: 3s 3:0 scan_limit 0000 r/w number of displayed segments in one frame (scanlimit) 0000: cs0 0001: cs0 to cs1 0010: cs0 to cs2 0011: cs0 to cs3 0100: cs0 to cs4 0101: cs0 to cs5 0110: cs0 to cs6 0111: cs0 to cs7 1000: cs0 to cs8 1001: cs0 to cs9 1010: cs0 to cs10 1011: cs0 to cs11 table 19. current source register format 0x05 current source register bit bit name default access bit description 7:0 current 00000000 r/w 00000000: 0ma .......... 11111111: 30ma ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 2 5 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n AS1130 config register (0x06) per default this register is set to 0x00. interrupt mask register (0x07) per default this register is set to 0x20. table 20. AS1130 config register format 0x06 AS1130 config register bit bit name default access bit description 7 low_vdd_rst 0 r/w 0: at the end of a movie or a display picture the low_v dd flag is not changed 1: at the end of a movie or a display picture, the low_v dd flag is set to 0 6 low_vdd_stat 0 r/w this bit indicates the supply status 0: if low_v dd is detected, the interrupt status register will be updated accordingly and pin irq is triggered. 1: the low_v dd bit is directly mapped to the pin irq. this can be used to control an external dc/dc converter or charge pump. in this case pin irq cant be used for interrupt functionality, the interrupt status register will be updated accordingly. 5 led_error_correction 0 r/w this bit defines the led open handling 0: open leds which are detected at led open test, are not disabled 1: open leds which are detected at led open test, are disabled 4 dot_corr 0 r/w analog current dotcorrection 1 0: disabled 1: enabled 1. this configuration is locked after the first write access to on/off, pwm od dotcorrection data section. unlock can be performed only by a reset of the device. 3 common_addr 0 r/w i2c common address 0: disabled 1: enabled (all AS1130 are reacting on the same address 0111111) 2:0 mem_conf 000 r/w define memory configuration 1 (see table 8 on page 14) 000: invalid configuration (default value) 001: ram configuration 1 010: ram configuration 2 011: ram configuration 3 100: ram configuration 4 101: ram configuration 5 110: ram configuration 6 table 21. interrupt mask register format 0x07 interrupt mask register bit bit name default access bit description 7 selected_pic 0 r/w irq pin triggers if defined frame is displayed (see interrupt frame d efinition register (0x08) on page 26) 0: disabled 1: enabled 6 watchdog 0 r/w irq pin triggers if the i2c watchdog triggers 0: disabled 1: enabled 5 por 1 r/w irq pin triggers if por is active 0: disabled 1: enabled ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 2 6 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n interrupt frame definition register (0x08) per default this register is set to 0x3f. shutdown & open/short register (0x09) per default this register is set to 0x02. 4 overtemp 0 r/w irq pin triggers if the over temperature limit is reached 0: disabled 1: enabled 3 low_vdd 0 r/w irq pin triggers if v dd is to low for used leds (low_v dd flag) 0: disabled 1: enabled 2 open_err 0 r/w irq pin triggers if an error on the open test occurs 0: disabled 1: enabled 1 short_err 0 r/w irq pin triggers if an error on the short test occurs 0: disabled 1: enabled 0 movie_fin 0 r/w irq pin triggers if a movie is finished 0: disabled 1: enabled table 22. interrupt frame definition register format 0x08 interrupt frame definition register bit bit name default access bit description 7:6 00 n/a 5:0 last_frame 111111 r/w after this frame is displayed the last time (depending on the number of loops played in a movie) an interrupt will be triggered. 000000: frame 0 000001: frame 1 000010: frame 2 000011: frame 3 000100: frame 4 000101: frame 5 .................. 100000: frame 32 100001: frame 33 100010: frame 34 100011: frame 35 table 23. shutdown & open/short register format 0x09 shutdown & open/short register bit bit name default access bit description 7:5 000 n/a 4 test_all 0 r/w the led open/short test is performed on all led locations 0: disabled 1: enabled table 21. interrupt mask register format 0x07 interrupt mask register bit bit name default access bit description ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 2 7 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n i2c interface monitoring register (0x0a) this register is used to monitor the activity on the i2c bus. if a deadlock situation occurs (e.g. the bus sda pin is pulled to low and no communi cation is possible) the chip will reset the i2c interface and the master is able to start the communication again. the time window for the reset of the interface of the AS1130 can bes set via 7 bits from 256s to 33ms. the default setting of this register is 0xff. clk synchronization register (0x0b) the default setting of this register is 0x00. 3 auto_test 0 r/w the led open/short test is automatically started at display picture/frame 0: disabled 1: enabled 2 manual_test 0 r/w the led open/short test is started manually 0: disabled 1: enabled 1 init 1 r/w 0: initialise control logic (internal state machine is reset again) 1: normal operation 0 shdn 0 r/w 0: device is in shutdown mode (outputs are turned off, internal state machine stops) 1: normal operation table 24. i2c interface monitoring register format 0x0a i2c interface monitoring register bit bit name default access bit description 7 1 n/a 6:1 time out window 11111 r/w definition of the time out window (0 to 127 => 1 to 128x256s) 0000000: 256s ........ 1111111: 32.7ms 0 i2c_monitor 1 r/w 0: i2c monitoring off 1: i2c monitoring on table 25. clk synchronization register format 0x0b clk synchronization register bit bit name default access bit description 7:4 0000 n/a 3:2 clk_out 00 r/w adjustable clock out frequency 00: 1mhz 01: 500khz 10: 125khz 11: 32khz table 23. shutdown & open/short register format 0x09 shutdown & open/short register bit bit name default access bit description ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 2 8 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n interrupt status register (0x0e) this is a read only register. within this register the cause of an interrupt can be read out. after power up or a reset the default setting of this reg ister is 0x20. a read out command will set this register to default and the irq pin will be released again. 1 sync_out 0 r/w the internal oscillator is used as systemclk. the selected clk frequency is available on pin d4 for synchronization. (output) 1 0: disabled 1: enabled 0 sync_in 0 r/w the internal oscillator is disabled. pin d4 is used as clk input for systemclk. 1 0: disabled 1: enabled 1. clk synchronization is done via the sync pin. only one option can be activated (input or output). table 26. interrupt status register format 0x0e interrupt status register bit bit name default access bit description 7 frame_int 0 r 0: no interrupt 1: defined frame is displayed (see interrupt frame definition r egister (0x08) on page 26) 6 i2c_int 0 r 0: no interrupt 1: i2c watchdog reports a deadlock on the interface 5 por_int 1 r 0: no interrupt 1: por was triggered 4 overtemp_int 0 r 0: no interrupt 1: over temperature limit is reached 3 low_vdd_int 0 r 0: no interrupt 1: v dd is too low to drive requested current through the leds 2 open_int 0 r 0: no interrupt 1: error on open test 1 short_int 0 r 0: no interrupt 1: error on short test 0 movie_int 0 r 0: no interrupt 1: play movie is finished table 25. clk synchronization register format 0x0b clk synchronization register bit bit name default access bit description ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 2 9 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n AS1130 status register (0x0f) this is a read only register. from this register the actual status of the AS1130 can be read out. the default setting of this register is 0x00. AS1130 open led register (0x20 to 0x37) this is a read only register. from this register the leds which failed with an open error can be read out. a 1 indicates led okay, a 0 stands for led open. if a led, which is physically not connected to the device is tested, the open led test will return a 0. table 27. AS1130 status register format 0x0f AS1130 status register bit bit name default access bit description 7:2 frame_on 000000 r actual displayed frame 000000: frame 0 000001: frame 1 000010: frame 2 000011: frame 3 000100: frame 4 000101: frame 5 ............... 100000: frame 32 100001: frame 33 100010: frame 34 100011: frame 35 1 movie_on 0 r 0: no movie 1: movie playing 0 test_on 0 r 0: no test is running 1: open/short test ongoing table 28. open led register format segment address data hex a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0x20 0 0 1 0 0 0 0 0 led 07 led 06 led 05 led 04 led 03 led 02 led 01 led 00 0x21 0 0 1 0 0 0 0 1 0 0 0 0 0 led 0a led 09 led 08 1 0x22 0 0 1 0 0 0 1 0 led 17 led 16 led 15 led 14 led 13 led 12 led 11 led 10 0x23 0 0 1 0 0 0 1 1 0 0 0 0 0 led 1a led 19 led 18 2 0x24 0 0 1 0 0 1 0 0 led 27 led 26 led 25 led 24 led 23 led 22 led 21 led 20 0x25 0 0 1 0 0 1 0 1 0 0 0 0 0 led 2a led 29 led 28 3 0x26 0 0 1 0 0 1 1 0 led 37 led 36 led 35 led 34 led 33 led 32 led 31 led 30 0x27 0 0 1 0 0 1 1 1 0 0 0 0 0 led 3a led 39 led 38 4 0x28 0 0 1 0 1 0 0 0 led 47 led 46 led 45 led 44 led 43 led 42 led 41 led 40 0x29 0 0 1 0 1 0 0 1 0 0 0 0 0 led 4a led 49 led 48 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 3 0 38 AS1130 datasheet r e g i s t e r d e s c r i p t i o n 5 0x2a 0 0 1 0 1 0 1 0 led 57 led 56 led 55 led 54 led 53 led 52 led 51 led 50 0x2b 0 0 1 0 1 0 1 1 0 0 0 0 0 led 5a led 59 led 58 6 0x2c 0 0 1 0 1 1 0 0 led 67 led 66 led 65 led 64 led 63 led 62 led 61 led 60 0x2d 0 0 1 0 1 1 0 1 0 0 0 0 0 led 6a led 69 led 68 7 0x2e 0 0 1 0 1 1 1 0 led 77 led 76 led 75 led 74 led 73 led 72 led 71 led 70 0x2f 0 0 1 0 1 1 1 1 0 0 0 0 0 led 7a led 79 led 78 8 0x30 0 0 1 1 0 0 0 0 led 87 led 86 led 85 led 84 led 83 led 82 led 81 led 80 0x31 0 0 1 1 0 0 0 1 0 0 0 0 0 led 8a led 89 led 88 9 0x32 0 0 1 1 0 0 1 0 led 97 led 96 led 95 led 94 led 93 led 92 led 91 led 90 0x33 0 0 1 1 0 0 1 1 0 0 0 0 0 led 9a led 99 led 98 a 0x34 0 0 1 1 0 1 0 0 led a7 led a6 led a5 led a4 led a3 led a2 led a1 led a0 0x35 0 0 1 1 0 1 0 1 0 0 0 0 0 led aa led a9 led a8 b 0x36 0 0 1 1 0 1 1 0 led b7 led b6 led b5 led b4 led b3 led b2 led b1 led b0 0x37 0 0 1 1 0 1 1 1 0 0 0 0 0 led ba led b9 led b8 table 28. open led register format segment address data hex a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 3 1 38 AS1130 datasheet ty p i c a l a p p l i c a t i o n 10 typical application scroll function the AS1130 offers a feature for scrolling a picture through the matrix without the need of communication via a p. the scrolling can be done in the whole matrix (11x12) or optimized for a ticker in a 5x24 matrix (see figure 25) . f igure 25. led configuration for 5led block scroll function in the movie display mode the frame is shown in the matrix at once. on the contrary in the scroll function the frame is shifted through the matrix segment after segment (cs0 to cs1 to cs2 to cs3 ......). figure 26. scrolling ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 3 2 38 AS1130 datasheet ty p i c a l a p p l i c a t i o n figure 27. ticker application with 5x96 led matrix ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 3 3 38 AS1130 datasheet ty p i c a l a p p l i c a t i o n led current calculation the current through a led in the matrix is set via three registers (current source register, dot correction and pwm). the resulting current through the single led can be calculated as shown in the following. first its necessary to calculate the time how long one led will be on. where: t ledon . . . . time where the led is on pwm . . . value set in the register (0 256), (see table 11 on page 18) f osc . . . frequency set in the clk synchronization register, (see table 25 on page 27) the refresh rate is defined by the scanlimit and f osc . where: t refresh . . . time needed to refresh the matrix scanlimit . . . is set via the display option register (0 11), (see table 18 on page 24) f osc . . . frequency set in the clk synchronization register, (see table 25 on page 27) with the led ontime and the refresh rate an average led on factor can be calculated. the resulting current is then the segment current (set in the current source register) times the average led on factor. where: i seg . . . segment current set via register (see table 19 on page 24) example: assume that following conditions are set in the registers: pwm = 256, scanlimit = 5 (half filled matrix, 66 leds), i seg = 30ma (eq 1) t ledon pwm f osc -------------- = (eq 2) t refresh scanlimit 1+ ( ) 256 f osc ------------------------------------------------------ = (eq 3) ledon avg t ledon t refresh ------------------------ pwm scanlimit 1+ ( ) 256 ------------------------------------------------------ = = (eq 4) i ledavg i seg ledon avg i seg pwm scanlimit 1+ ( ) 256 ------------------------------------------------------ = = (eq 5) i ledavg 30 ma 256 5 1+ ( ) 256 -------------------------------- 5 ma = = ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 3 4 38 AS1130 datasheet p a c k a g e d r a w i n g s a n d m a r k i n g s 11 package drawings and markings figure 28. 20-pin wl-csp marking figure 29. 28-pin ssop marking table 29. packaging code yywwrzz yy ww r zz last two digits of the current year manufacturing week plant identifier free choice / traceability code ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 3 5 38 AS1130 datasheet p a c k a g e d r a w i n g s a n d m a r k i n g s figure 30. 20-pin wl-csp package ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 3 6 38 AS1130 datasheet p a c k a g e d r a w i n g s a n d m a r k i n g s figure 31. 28-pin ssop package ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 3 7 38 AS1130 datasheet o r d e r i n g i n f o r m a t i o n 12 ordering information the devices are available as the standard products shown in table 30 . * ) on request note: all products are rohs compliant and austriamicrosystems green. buy our products or get free samples online at icdirect: http://www.austriamicrosystems.com/icdirect technical support is found at http://www.austriamicrosystems.com/technicalsupport for further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor table 30. ordering information ordering code marking logic levels address description delivery form package AS1130bsst AS1130 cmos 0x30 0x37 132led crossplexing driver with scrolling function tape and reel 28pin ssop AS1130bbsst* AS1130b mobile 132led crossplexing driver with scrolling function tape and reel AS1130cbsst* AS1130c cmos 0x38 0x3e 132led crossplexing driver with scrolling function tape and reel AS1130dbsst* AS1130d mobile 132led crossplexing driver with scrolling function tape and reel AS1130bwlt AS1130 cmos 0x30 0x37 132led crossplexing driver with scrolling function tape and reel 20pin wlcsp AS1130bbwlt* AS1130b mobile 132led crossplexing driver with scrolling function tape and reel AS1130cbwlt* tbd cmos 0x38 0x3e 132led crossplexing driver with scrolling function tape and reel AS1130dbwlt* tbd mobile 132led crossplexing driver with scrolling function tape and reel ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/AS1130 revision 1.07 3 8 38 AS1130 datasheet copyrights copyright ? 19972012, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austriaeurope. trademarks registered ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. aus triamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical lifesupport or lifesustaining equipment are specif ically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact ams ag technical content still valid

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